The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Mar. 08, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hsuan-Han Lin, Kaohsiung, TW;

Jhu-Ming Song, Nantou, TW;

Mu-Yi Lin, Taichung, TW;

Kuang-Hsin Chen, Jung-Li, TW;

Bor-Zen Tien, Hsin-Chu, TW;

Tzong-Sheng Chang, Chubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76807 (2013.01); H01L 21/76843 (2013.01); H01L 23/53238 (2013.01); H01L 24/00 (2013.01); H01L 21/2855 (2013.01); H01L 21/28562 (2013.01); H01L 23/53228 (2013.01); H01L 2221/1015 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.


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