The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Dec. 27, 2012
Applicant:

Xintec Inc., Jhongli, TW;

Inventors:

Yen-Shih Ho, Jhongli, TW;

Hsin Kuan, Jhongli, TW;

Long-Sheng Yeou, Jhongli, TW;

Tsang-Yu Liu, Jhongli, TW;

Chia-Ming Cheng, Jhongli, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 21/78 (2006.01); H01L 23/48 (2006.01); H01L 23/28 (2006.01); H01L 21/82 (2006.01); H01L 23/14 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); B81B 7/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); B81B 7/007 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 21/76898 (2013.01); H01L 23/14 (2013.01); H01L 23/147 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); B81B 2207/096 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68304 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68363 (2013.01); H01L 2221/68368 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24051 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/92 (2013.01); H01L 2224/97 (2013.01); H01L 2924/1461 (2013.01);
Abstract

A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.


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