The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Sep. 30, 2013
Chia-pin Chiu, Tempe, AZ (US);
Qing MA, Saratoga, CA (US);
Robert L. Sankman, Phoenix, AZ (US);
Paul B. Fischer, Portland, OR (US);
Patrick Morrow, Portland, OR (US);
William J. Lambert, Chandler, AZ (US);
Charles A. Gealer, Phoenix, AZ (US);
Tyler Osborn, Gilbert, AZ (US);
Chia-Pin Chiu, Tempe, AZ (US);
Qing Ma, Saratoga, CA (US);
Robert L. Sankman, Phoenix, AZ (US);
Paul B. Fischer, Portland, OR (US);
Patrick Morrow, Portland, OR (US);
William J. Lambert, Chandler, AZ (US);
Charles A. Gealer, Phoenix, AZ (US);
Tyler Osborn, Gilbert, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.