The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2015
Filed:
Apr. 18, 2013
Applied Materials, Inc., Santa Clara, CA (US);
Xinliang Lu, Fremont, CA (US);
Seshadri Ganguli, Sunnyvale, CA (US);
Atif Noori, Saratoga, CA (US);
Maitreyee Mahajani, Saratoga, CA (US);
Shih Chung Chen, Cupertino, CA (US);
Yu Lei, Foster City, CA (US);
Xinyu Fu, Fremont, CA (US);
Wei Tang, Santa Clara, CA (US);
Srinivas Gandikota, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.