The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2015
Filed:
Oct. 24, 2013
Rohm and Haas Electronic Materials Cmp Holdings, Inc., Newark, DE (US);
Nitta Haas Incorporated, Osaka, JP;
Yasuyuki Itai, Kyoto, JP;
Bainian Qian, Newark, DE (US);
Hiroyuki Nakano, Kyotanabe, JP;
David B. James, Newark, DE (US);
Naoko Kawai, Kyoto, JP;
Katsumasa Kawabata, Kyoto, JP;
Koichi Yoshida, Kyoto, JP;
Kazutaka Miyamoto, Mie, JP;
James Murnane, Norristown, PA (US);
Fengji Yeh, Wilmington, DE (US);
Marty W. DeGroot, Middletown, DE (US);
Rohm and Haas Electronic Materials CMP Holdings, Inc., Newark, DE (US);
Nitta Haas Incorporated, Osaka, JP;
Abstract
A method for polishing a silicon wafer is provided, comprising: providing a silicon wafer; providing a polishing pad having a polishing layer which is the reaction product of raw material ingredients, including: a polyfunctional isocyanate; and, a curative package; wherein the curative package contains an amine initiated polyol curative and a high molecular weight polyol curative; wherein the polishing layer exhibits a density of greater than 0.4 g/cm; a Shore D hardness of 5 to 40; an elongation to break of 100 to 450%; and, a cut rate of 25 to 150 μm/hr; and, wherein the polishing layer has a polishing surface adapted for polishing the silicon wafer; and, creating dynamic contact between the polishing surface and the silicon wafer.