The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2015
Filed:
May. 13, 2013
Tieyu Zheng, Redmond, WA (US);
Sumit Kumar, Phoenix, AZ (US);
Sridhar Nara, San Jose, CA (US);
Renee D. Garcia, Gilbert, AZ (US);
Manohar S. Konchady, Chandler, AZ (US);
Suresh B. Yeruva, Chandler, AZ (US);
Lynn H. Chen, Gilbert, AZ (US);
Tyler N. Osborn, Gilbert, AZ (US);
Sairam Agraharam, Chandler, AZ (US);
Tieyu Zheng, Redmond, WA (US);
Sumit Kumar, Phoenix, AZ (US);
Sridhar Nara, San Jose, CA (US);
Renee D. Garcia, Gilbert, AZ (US);
Manohar S. Konchady, Chandler, AZ (US);
Suresh B. Yeruva, Chandler, AZ (US);
Lynn H. Chen, Gilbert, AZ (US);
Tyler N. Osborn, Gilbert, AZ (US);
Sairam Agraharam, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).