The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
Aug. 08, 2012
Hsin-an Shen, Hsin-Chu, TW;
Yung Ching Chen, Dali, TW;
Ming-chung Sung, Taichung, TW;
Chih-hang Tung, Hsin-Chu, TW;
Chien-hsun Lee, Chu-tung Town, TW;
Da-yuan Shih, Hsin-Chu, TW;
Hsin-An Shen, Hsin-Chu, TW;
Yung Ching Chen, Dali, TW;
Ming-Chung Sung, Taichung, TW;
Chih-Hang Tung, Hsin-Chu, TW;
Chien-Hsun Lee, Chu-tung Town, TW;
Da-Yuan Shih, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Disclosed herein is a system and method for mounting packages by forming one or more wire loop interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a first substrate. A first and second stud ball may each have at least one flat surface be disposed on a single mounting pad, and a wire having a bend region and forming a loop may be disposed between the stud balls. The stud balls may be formed from a deformed mouthing node formed on a wire. The loop may be mounted on a mounting pad on a first substrate and a second substrate may be mounted on the loop via a conductive material such as solder.