The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Jan. 10, 2013
Po-shen Lin, Jhongli, TW;
Chuan-jin Shiu, Jhongli, TW;
Bing-siang Chen, Jhongli, TW;
Chen-han Chiang, Jhongli, TW;
Chien-hui Chen, Jhongli, TW;
Hsi-chien Lin, Jhongli, TW;
Yen-shih Ho, Jhongli, TW;
Po-Shen Lin, Jhongli, TW;
Chuan-Jin Shiu, Jhongli, TW;
Bing-Siang Chen, Jhongli, TW;
Chen-Han Chiang, Jhongli, TW;
Chien-Hui Chen, Jhongli, TW;
Hsi-Chien Lin, Jhongli, TW;
Yen-Shih Ho, Jhongli, TW;
Xintec Inc., Jhongli, TW;
Abstract
A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided.