The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2014

Filed:

Mar. 09, 2012
Applicants:

Clement Hsingjen Wann, Carmel, NY (US);

Chih-sheng Chang, Hsinchu, TW;

Yi-tang Lin, Hsinchu, TW;

Ming-feng Shieh, Yongkang, TW;

Ting-chu Ko, Hsinchu, TW;

Chung-hsien Chen, Taipei, TW;

Inventors:

Clement Hsingjen Wann, Carmel, NY (US);

Chih-Sheng Chang, Hsinchu, TW;

Yi-Tang Lin, Hsinchu, TW;

Ming-Feng Shieh, Yongkang, TW;

Ting-Chu Ko, Hsinchu, TW;

Chung-Hsien Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Published as:
CN102760732A; US2012273899A1; US8816444B2; US2014332904A1; CN102760732B; US9634001B2;

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