The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Jul. 28, 2014
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Chih-Sheng Chang, Hsinchu, TW;
Yi-Tang Lin, Hsinchu, TW;
Ming-Feng Shieh, Yongkang, TW;
Ting-Chu Ko, Hsinchu, TW;
Chung-Hsien Chen, Taipei, TW;
Abstract
A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction.