The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

Nov. 18, 2011
Applicants:

Maryjane Brodsky, Salt Point, NY (US);

Murshed M. Chowdhury, Newburgh, NY (US);

Michael P. Chudzik, Danbury, CT (US);

Min Dai, Mahwah, NJ (US);

Siddarth A. Krishnan, Peekskill, NY (US);

Shreesh Narasimha, Beacon, NY (US);

Shahab Siddiqui, White Plains, NY (US);

Inventors:

MaryJane Brodsky, Salt Point, NY (US);

Murshed M. Chowdhury, Newburgh, NY (US);

Michael P. Chudzik, Danbury, CT (US);

Min Dai, Mahwah, NJ (US);

Siddarth A. Krishnan, Peekskill, NY (US);

Shreesh Narasimha, Beacon, NY (US);

Shahab Siddiqui, White Plains, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.


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