The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2014
Filed:
Dec. 22, 2011
Chia-en Huang, Xinfeng Township, TW;
Wun-jie Lin, Hsin-Chu, TW;
Ling-chang HU, Lugang Township, TW;
Hsiao-lan Yang, Taipei, TW;
Chih-chieh Chiu, Toufen Township, TW;
Wei-shuo Kao, Taichuang, TW;
Hong-chen Cheng, Hsin-Chu, TW;
Fu-an Wu, Hsin-Chu, TW;
Jung-ping Yang, Juibei, TW;
Cheng Hung Lee, Hsin-Chu, TW;
Chia-En Huang, Xinfeng Township, TW;
Wun-Jie Lin, Hsin-Chu, TW;
Ling-Chang Hu, Lugang Township, TW;
Hsiao-Lan Yang, Taipei, TW;
Chih-Chieh Chiu, Toufen Township, TW;
Wei-Shuo Kao, Taichuang, TW;
Hong-Chen Cheng, Hsin-Chu, TW;
Fu-An Wu, Hsin-Chu, TW;
Jung-Ping Yang, Juibei, TW;
Cheng Hung Lee, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.