The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2013
Filed:
May. 14, 2010
Koichi Hayakawa, Hitachinaka, JP;
Takehiro Hirai, Ushiku, JP;
Yutaka Tandai, Hitachinaka, JP;
Tamao Ishikawa, Hitachinaka, JP;
Tsunehiro Sakai, Mito, JP;
Kazuhisa Hasumi, Hitachinaka, JP;
Kazunori Nemoto, Akishima, JP;
Katsuhiko Ichinose, Tokorozawa, JP;
Yuji Takagi, Kamakura, JP;
Koichi Hayakawa, Hitachinaka, JP;
Takehiro Hirai, Ushiku, JP;
Yutaka Tandai, Hitachinaka, JP;
Tamao Ishikawa, Hitachinaka, JP;
Tsunehiro Sakai, Mito, JP;
Kazuhisa Hasumi, Hitachinaka, JP;
Kazunori Nemoto, Akishima, JP;
Katsuhiko Ichinose, Tokorozawa, JP;
Yuji Takagi, Kamakura, JP;
Hitachi High-Technologies Corporation, Tokyo, JP;
Abstract
A defect is efficiently and effectively classified by accurately determining the state of overlap between a design layout pattern and the defect. This leads to simple identification of a systematic defect. A defective image obtained through defect inspection or review of a semiconductor device is automatically pattern-matched with design layout data. A defect is superimposed on a design layout pattern for at least one layer of a target layer, a layer immediately above the target layer, and a layer immediately below the target layer. The state of overlap of the defect is determined as within the pattern, over the pattern, or outside the pattern, and the defect is automatically classified.