The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2013

Filed:

Nov. 16, 2011
Applicants:

Chin-i Liao, Tainan, TW;

Chia-lin Hsu, Tainan, TW;

Ming-yen LI, Taichung, TW;

Min-ying Hsu, Tainan, TW;

Hsin-huei Wu, Chiayi, TW;

Yung-lun Hsieh, Tainan, TW;

Chien-hao Chen, Yun-Lin County, TW;

Bo-syuan Lee, Tainan, TW;

Inventors:

Chin-I Liao, Tainan, TW;

Chia-Lin Hsu, Tainan, TW;

Ming-Yen Li, Taichung, TW;

Min-Ying Hsu, Tainan, TW;

Hsin-Huei Wu, Chiayi, TW;

Yung-Lun Hsieh, Tainan, TW;

Chien-Hao Chen, Yun-Lin County, TW;

Bo-Syuan Lee, Tainan, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.


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