Tainan, Taiwan

Min-Ying Hsu

This inventor holds 1 USPTO granted patent. Top assignee: United Microelectronics Corp.. Active years: 2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Min-Ying Hsu. Retrieved from https://idiyas.com/inventor/min-ying-hsu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 8.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2013

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1 patent (USPTO):Explore Patents

Title: Min-Ying Hsu and His Multi-Gate Transistor Patent.

Introduction

Min-Ying Hsu is an inventor associated with Tainan, Taiwan, and United Microelectronics Corp. His patent work includes a method for manufacturing a multi-gate transistor device.

Latest Patents

Hsu is listed as an inventor on 1 patent: “Method for Manufacturing Multi-Gate Transistor Device.” The method describes providing a semiconductor substrate with a patterned semiconductor layer and patterned hard mask, removing the hard mask, and thermally treating the semiconductor layer at a temperature below 800°C to round its shape. A gate dielectric layer and gate layer are then formed over part of the patterned semiconductor layer.

Career Highlights

Hsu’s listed invention concerns semiconductor device fabrication, specifically the formation of a multi-gate transistor structure. The patent identifies United Microelectronics Corp. as his company affiliation.

Collaborations

Chia-Lin Hsu and Yung-Lun Hsieh are identified as Hsu’s coworkers. Their names are provided as professional associations, without further details about their roles in this patent.

Conclusion

Min-Ying Hsu’s patent documents a semiconductor manufacturing method that uses low-temperature thermal treatment to shape a patterned layer before gate formation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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