The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2013
Filed:
Oct. 14, 2010
Wei-yen Woon, Taoyuan, TW;
Chun-feng Nieh, Baoshan Township, TW;
Ching-yi Chen, Hsin-Chu, TW;
Hsun Chang, Hsin-Chu, TW;
Chung-ru Yang, Chung-Ho, TW;
Li-te S. Lin, Hsin-Chu, TW;
Wei-Yen Woon, Taoyuan, TW;
Chun-Feng Nieh, Baoshan Township, TW;
Ching-Yi Chen, Hsin-Chu, TW;
Hsun Chang, Hsin-Chu, TW;
Chung-Ru Yang, Chung-Ho, TW;
Li-Te S. Lin, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.