The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2013
Filed:
Dec. 23, 2010
Chang Ju Choi, Fremont, CA (US);
Cheng-hsin MA, Redwood City, CA (US);
Sven Henrichs, San Jose, CA (US);
Robert H. Olshausen, Menlo Park, CA (US);
Yulia Korobko, Saratoga, CA (US);
Chang Ju Choi, Fremont, CA (US);
Cheng-Hsin Ma, Redwood City, CA (US);
Sven Henrichs, San Jose, CA (US);
Robert H. Olshausen, Menlo Park, CA (US);
Yulia Korobko, Saratoga, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.