The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2012

Filed:

Dec. 22, 2010
Applicants:

Nagarajan Rajagopalan, Santa Clara, CA (US);

Ji AE Park, Santa Clara, CA (US);

Ryan Yamase, Santa Clara, CA (US);

Shamik Patel, Redlands, CA (US);

Thomas Nowak, Cupertino, CA (US);

Li-qun Xia, Cupertino, CA (US);

Bok Hoen Kim, San Jose, CA (US);

Ran Ding, Sunnyvale, CA (US);

Jim Baldino, Portland, OR (US);

Mehul Naik, San Jose, CA (US);

Sesh Ramaswami, Saratoga, CA (US);

Inventors:

Nagarajan Rajagopalan, Santa Clara, CA (US);

Ji Ae Park, Santa Clara, CA (US);

Ryan Yamase, Santa Clara, CA (US);

Shamik Patel, Redlands, CA (US);

Thomas Nowak, Cupertino, CA (US);

Li-Qun Xia, Cupertino, CA (US);

Bok Hoen Kim, San Jose, CA (US);

Ran Ding, Sunnyvale, CA (US);

Jim Baldino, Portland, OR (US);

Mehul Naik, San Jose, CA (US);

Sesh Ramaswami, Saratoga, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/44 (2006.01); H01L 21/31 (2006.01);
U.S. Cl.
CPC ...
Abstract

A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.


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