The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2012
Filed:
Dec. 23, 2010
Nagarajan Rajagopalan, Santa Clara, CA (US);
Ji AE Park, Santa Clara, CA (US);
Ryan Yamase, Santa Clara, CA (US);
Shamik Patel, Redlands, CA (US);
Thomas Nowak, Cupertino, CA (US);
Li-qun Xia, Cupertino, CA (US);
Bok Hoen Kim, San Jose, CA (US);
Ran Ding, Sunnyvale, CA (US);
Jim Baldino, Portland, OR (US);
Mehul Naik, San Jose, CA (US);
Sesh Ramaswami, Saratoga, CA (US);
Nagarajan Rajagopalan, Santa Clara, CA (US);
Ji Ae Park, Santa Clara, CA (US);
Ryan Yamase, Santa Clara, CA (US);
Shamik Patel, Redlands, CA (US);
Thomas Nowak, Cupertino, CA (US);
Li-Qun Xia, Cupertino, CA (US);
Bok Hoen Kim, San Jose, CA (US);
Ran Ding, Sunnyvale, CA (US);
Jim Baldino, Portland, OR (US);
Mehul Naik, San Jose, CA (US);
Sesh Ramaswami, Saratoga, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.