The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2011

Filed:

Jun. 08, 2009
Applicants:

Nathapong Suthiwongsunthorn, Singapore, SG;

Pandi C. Marimuthu, Singapore, SG;

Jae Hun Ku, Singapore, SG;

Glenn Omandam, Singapore, SG;

Hin Hwa Goh, Singapore, SG;

Kock Liang Heng, Singapore, SG;

Jose A. Caparas, Singapore, SG;

Inventors:

Nathapong Suthiwongsunthorn, Singapore, SG;

Pandi C. Marimuthu, Singapore, SG;

Jae Hun Ku, Singapore, SG;

Glenn Omandam, Singapore, SG;

Hin Hwa Goh, Singapore, SG;

Kock Liang Heng, Singapore, SG;

Jose A. Caparas, Singapore, SG;

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device has a conductive via formed through in a first side of the substrate. A first interconnect structure is formed over the first side of the substrate. A semiconductor die or component is mounted to the first interconnect structure. An encapsulant is deposited over the first interconnect structure and semiconductor die or component. A portion of a second side of the substrate is removed to reduce its thickness and expose the TSV. A second interconnect structure is formed over the second side of the substrate. The encapsulant provides structural support while removing the portion of the second side of the substrate. The second interconnect structure is electrically connected to the conductive via. The second interconnect structure can include a redistribution layer to extend the conductivity of the conductive via. The semiconductor device is mounted to a printed circuit board through the second interconnect structure.


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