The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2010
Filed:
Feb. 13, 2003
Michael Adel, Zichron Ya'akov, IL;
Mark Ghinovker, Migdal Haemek, IL;
Elyakim Kassel, D.N. Misgav, IL;
Boris Golovanevsky, Haifa, IL;
John C. Robinson, Austin, TX (US);
Chris A. Mack, Austin, TX (US);
Jorge Poplawski, Haifa, IL;
Pavel Izikson, Haifa, IL;
Moshe Preil, Sunnyvale, CA (US);
Michael Adel, Zichron Ya'akov, IL;
Mark Ghinovker, Migdal Haemek, IL;
Elyakim Kassel, D.N. Misgav, IL;
Boris Golovanevsky, Haifa, IL;
John C. Robinson, Austin, TX (US);
Chris A. Mack, Austin, TX (US);
Jorge Poplawski, Haifa, IL;
Pavel Izikson, Haifa, IL;
Moshe Preil, Sunnyvale, CA (US);
KLA-Tencor Technologies Corporation, Milpitas, CA (US);
Abstract
An overlay method for determining the overlay error of a device structure formed during semiconductor processing is disclosed. The overlay method includes producing calibration data that contains overlay information relating the overlay error of a first target at a first location to the overlay error of a second target at a second location for a given set of process conditions. The overlay method also includes producing production data that contains overlay information associated with a production target formed with the device structure. The overlay method further includes correcting the overlay error of the production target based on the calibration data.