The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Dec. 26, 2006
Min-lung Huang, Kaohsiung, TW;
Wei-chung Wang, Kaohsiung, TW;
Po-jen Cheng, Kaohsiung, TW;
Kuo-chung Yee, Kaohsiung, TW;
Ching-huei Su, Kaohsiung, TW;
Jian-wen Lo, Kaohsiung, TW;
Chian-chi Lin, Kaohsiung, TW;
Min-Lung Huang, Kaohsiung, TW;
Wei-Chung Wang, Kaohsiung, TW;
Po-Jen Cheng, Kaohsiung, TW;
Kuo-Chung Yee, Kaohsiung, TW;
Ching-Huei Su, Kaohsiung, TW;
Jian-Wen Lo, Kaohsiung, TW;
Chian-Chi Lin, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.