The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
May. 27, 2006
Kuang-hsin Chen, Hsin-Chu, TW;
Hsun-chih Tsao, Hsin-Chu, TW;
Jhi-cherng LU, Taipei, TW;
Chuan-ping Hou, Yungkang, TW;
Peng-fu Hsu, Hsinchu, TW;
Hung-wei Chen, Hsinchu, TW;
Di-hong Lee, Hsin-Chu, TW;
Kuang-Hsin Chen, Hsin-Chu, TW;
Hsun-Chih Tsao, Hsin-Chu, TW;
Jhi-Cherng Lu, Taipei, TW;
Chuan-Ping Hou, Yungkang, TW;
Peng-Fu Hsu, Hsinchu, TW;
Hung-Wei Chen, Hsinchu, TW;
Di-Hong Lee, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co, Ltd, Hsin-Chu, TW;
Abstract
A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.