The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Jan. 22, 2007
Chen-shien Chen, Hsinchu, TW;
Kuo-chin Chang, Hsinchu, TW;
Szu-wei LU, Hsinchu, TW;
Pei-haw Tsao, Taichung, TW;
Chung-yu Wang, Hsinchu, TW;
Han-liang Tseng, Hsinchu, TW;
Mirng-ji Lii, Hsinchu, TW;
Chen-Shien Chen, Hsinchu, TW;
Kuo-Chin Chang, Hsinchu, TW;
Szu-Wei Lu, Hsinchu, TW;
Pei-Haw Tsao, Taichung, TW;
Chung-Yu Wang, Hsinchu, TW;
Han-Liang Tseng, Hsinchu, TW;
Mirng-Ji Lii, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.