The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2010
Filed:
Jun. 24, 2008
Ricky S. Amos, Rhinebeck, NY (US);
Diane C. Boyd, LaGrangeville, NY (US);
Cyril Cabral, Jr., Mahopac, NY (US);
Richard D. Kaplan, Wappingers Falls, NY (US);
Jakub T. Kedzierski, Peekskill, NY (US);
Victor Ku, Tarrytown, NY (US);
Woo-hyeong Lee, Poughquag, NY (US);
Ying LI, Pougkeepsie, NY (US);
Anda C. Mocuta, LaGrangeville, NY (US);
Vijay Narayanan, New York, NY (US);
An L. Steegen, Stanford, CT (US);
Maheswaren Surendra, Croton-on-Hudson, NY (US);
Ricky S. Amos, Rhinebeck, NY (US);
Diane C. Boyd, LaGrangeville, NY (US);
Cyril Cabral, Jr., Mahopac, NY (US);
Richard D. Kaplan, Wappingers Falls, NY (US);
Jakub T. Kedzierski, Peekskill, NY (US);
Victor Ku, Tarrytown, NY (US);
Woo-Hyeong Lee, Poughquag, NY (US);
Ying Li, Pougkeepsie, NY (US);
Anda C. Mocuta, LaGrangeville, NY (US);
Vijay Narayanan, New York, NY (US);
An L. Steegen, Stanford, CT (US);
Maheswaren Surendra, Croton-on-Hudson, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.