The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2010
Filed:
Oct. 23, 2006
Min-lung Huang, Kaohsiung, TW;
Wei-chung Wang, Kaohsiung, TW;
Po-jen Cheng, Kaohsiung, TW;
Kuo-chung Yee, Kaohsiung, TW;
Ching-huei Su, Kaohsiung, TW;
Jian-wen Lo, Kaohsiung, TW;
Chian-chi Lin, Kaohsiung, TW;
Min-Lung Huang, Kaohsiung, TW;
Wei-Chung Wang, Kaohsiung, TW;
Po-Jen Cheng, Kaohsiung, TW;
Kuo-Chung Yee, Kaohsiung, TW;
Ching-Huei Su, Kaohsiung, TW;
Jian-Wen Lo, Kaohsiung, TW;
Chian-Chi Lin, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are 'inserted' into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.