The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2009

Filed:

Dec. 19, 2007
Applicants:

Kaushik Chanda, Fishkill, NY (US);

Birendra Agarwala, Hopewell Junction, NY (US);

Lawrence A. Clevenger, La Grangeville, NY (US);

Andrew P. Cowley, Wappingers Falls, NY (US);

Ronald G. Filippi, Wappingers Falls, NY (US);

Jason P. Gill, Essex Junction, VT (US);

Tom C. Lee, Essex Junction, VT (US);

Baozhen LI, South Burlington, VT (US);

Paul S. Mclaughlin, Poughkeepsie, NY (US);

Du B. Nguyen, Danbury, CT (US);

Hazara S. Rathore, Stormville, NY (US);

Timothy D. Sullivan, Underhill, VT (US);

Chih-chao Yang, Poughkeepsie, NY (US);

Inventors:

Kaushik Chanda, Fishkill, NY (US);

Birendra Agarwala, Hopewell Junction, NY (US);

Lawrence A. Clevenger, La Grangeville, NY (US);

Andrew P. Cowley, Wappingers Falls, NY (US);

Ronald G. Filippi, Wappingers Falls, NY (US);

Jason P. Gill, Essex Junction, VT (US);

Tom C. Lee, Essex Junction, VT (US);

Baozhen Li, South Burlington, VT (US);

Paul S. McLaughlin, Poughkeepsie, NY (US);

Du B. Nguyen, Danbury, CT (US);

Hazara S. Rathore, Stormville, NY (US);

Timothy D. Sullivan, Underhill, VT (US);

Chih-Chao Yang, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01); H01L 23/58 (2006.01); G01N 25/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).


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