The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2009
Filed:
Dec. 05, 2006
Shyh-fann Ting, Kao-Hsiung Hsien, TW;
Cheng-tung Huang, Kao-Hsiung, TW;
Jing-chang Wu, Yun-Lin Hsien, TW;
Kun-hsien Lee, Tai-Nan, TW;
Wen-han Hung, Kao-Hsiung, TW;
Li-shian Jeng, Tai-Tung Hsien, TW;
Tzer-min Shen, Hsin-Chu, TW;
Tzyy-ming Cheng, Hsin-Chu, TW;
Nien-chung LI, Hsin-Chu, TW;
Shyh-Fann Ting, Kao-Hsiung Hsien, TW;
Cheng-Tung Huang, Kao-Hsiung, TW;
Jing-Chang Wu, Yun-Lin Hsien, TW;
Kun-Hsien Lee, Tai-Nan, TW;
Wen-Han Hung, Kao-Hsiung, TW;
Li-Shian Jeng, Tai-Tung Hsien, TW;
Tzer-Min Shen, Hsin-Chu, TW;
Tzyy-Ming Cheng, Hsin-Chu, TW;
Nien-Chung Li, Hsin-Chu, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source/drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.