The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Dec. 26, 2006
Min-lung Huang, Kaohsiung, TW;
Wei-chung Wang, Kaohsiung, TW;
Po-jen Cheng, Kaohsiung, TW;
Kuo-chung Yee, Kaohsiung, TW;
Ching-huei Su, Kaohsiung, TW;
Jian-wen Lo, Kaohsiung, TW;
Chian-chi Lin, Kaohsiung, TW;
Min-Lung Huang, Kaohsiung, TW;
Wei-Chung Wang, Kaohsiung, TW;
Po-Jen Cheng, Kaohsiung, TW;
Kuo-Chung Yee, Kaohsiung, TW;
Ching-Huei Su, Kaohsiung, TW;
Jian-Wen Lo, Kaohsiung, TW;
Chian-Chi Lin, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.