The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2008
Filed:
Dec. 26, 2006
Min-lung Huang, Kaohsiung, TW;
Wei-chung Wang, Kaohsiung, TW;
Po-jen Cheng, Kaohsiung, TW;
Kuo-chung Yee, Kaohsiung, TW;
Ching-huei Su, Kaohsiung, TW;
Jian-wen Lo, Kaohsiung, TW;
Chian-chi Lin, Kaohsiung, TW;
Min-Lung Huang, Kaohsiung, TW;
Wei-Chung Wang, Kaohsiung, TW;
Po-Jen Cheng, Kaohsiung, TW;
Kuo-Chung Yee, Kaohsiung, TW;
Ching-Huei Su, Kaohsiung, TW;
Jian-Wen Lo, Kaohsiung, TW;
Chian-Chi Lin, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaoshiung, TW;
Abstract
A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.