The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2008
Filed:
Dec. 17, 2006
Chien-li Kuo, Hsin-Chu, TW;
Ping-chang Wu, Hsin-Chu Hsien, TW;
Jui-meng Jao, Miao- Li Hsien, TW;
Hui-ling Chen, Kao-Hsiung Hsien, TW;
Kai-kuang Ho, Hsin-Chu, TW;
Ching-li Yang, Ping-Tung Hsien, TW;
Chien-Li Kuo, Hsin-Chu, TW;
Ping-Chang Wu, Hsin-Chu Hsien, TW;
Jui-Meng Jao, Miao- Li Hsien, TW;
Hui-Ling Chen, Kao-Hsiung Hsien, TW;
Kai-Kuang Ho, Hsin-Chu, TW;
Ching-Li Yang, Ping-Tung Hsien, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.