The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2008
Filed:
Nov. 17, 2005
Jei-ming Chen, Taipei Hsien, TW;
Miao-chun Lin, Tainan Hsien, TW;
Kuo-chih Lai, Tai-Nan, TW;
Mei-ling Chen, Kao-Hsiung, TW;
Cheng-ming Weng, Hsin-Chu Hsien, TW;
Chun-jen Huang, Tainan Hsien, TW;
Yu-tsung Lai, Tai-Chung Hsien, TW;
Jei-Ming Chen, Taipei Hsien, TW;
Miao-Chun Lin, Tainan Hsien, TW;
Kuo-Chih Lai, Tai-Nan, TW;
Mei-Ling Chen, Kao-Hsiung, TW;
Cheng-Ming Weng, Hsin-Chu Hsien, TW;
Chun-Jen Huang, Tainan Hsien, TW;
Yu-Tsung Lai, Tai-Chung Hsien, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×10atoms/cm. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.