The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2007
Filed:
May. 04, 2005
Khee Yong Lim, Singapore, SG;
Wenhe Lin, Singapore, SG;
Chung Woh Lai, Singapore, SG;
Yong Meng Lee, Singapore, SG;
Liang Choo Hsia, Singapore, SG;
Young Way Teh, Singapore, SG;
John Sudijono, Singapore, SG;
Wee Leng Tan, Singapore, SG;
Hui Peng Koh, Singapore, SG;
Khee Yong Lim, Singapore, SG;
Wenhe Lin, Singapore, SG;
Chung Woh Lai, Singapore, SG;
Yong Meng Lee, Singapore, SG;
Liang Choo Hsia, Singapore, SG;
Young Way Teh, Singapore, SG;
John Sudijono, Singapore, SG;
Wee Leng Tan, Singapore, SG;
Hui Peng Koh, Singapore, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.