The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2007
Filed:
Jul. 06, 2004
Justin K. Brask, Portland, OR (US);
Chris E. Barns, Portland, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Uday Shah, Portland, OR (US);
Jack Kavalieros, Portland, OR (US);
Matthew V. Metz, Hillsboro, OR (US);
Suman Datta, Beaverton, OR (US);
Anne E. Miller, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Justin K. Brask, Portland, OR (US);
Chris E. Barns, Portland, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Uday Shah, Portland, OR (US);
Jack Kavalieros, Portland, OR (US);
Matthew V. Metz, Hillsboro, OR (US);
Suman Datta, Beaverton, OR (US);
Anne E. Miller, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.