The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2005

Filed:

Apr. 26, 2001
Applicants:

Kazuhisa Mochida, Saitama, JP;

Katsumi Togasaki, Saitama, JP;

Katsumi Morita, Saitama, JP;

Yusuke Masutani, Saitama, JP;

Hiroji Kameda, Saitama, JP;

Noboru Sekiguchi, Saitama, JP;

Minoru Shimada, Saitama, JP;

Toshio Toyama, Saitama, JP;

Akihiro Koga, Saitama, JP;

Mitsuo Inoue, Saitama, JP;

Kazuhiro Abe, Saitama, JP;

Tetsuya Yonemoto, Saitama, JP;

Kenji Ishihara, Saitama, JP;

Syunji Aoki, Saitama, JP;

Fumio Matsumoto, Saitama, JP;

Takanori Arai, Saitama, JP;

Hisashi Naoshima, Saitama, JP;

Inventors:

Kazuhisa Mochida, Saitama, JP;

Katsumi Togasaki, Saitama, JP;

Katsumi Morita, Saitama, JP;

Yusuke Masutani, Saitama, JP;

Hiroji Kameda, Saitama, JP;

Noboru Sekiguchi, Saitama, JP;

Minoru Shimada, Saitama, JP;

Toshio Toyama, Saitama, JP;

Akihiro Koga, Saitama, JP;

Mitsuo Inoue, Saitama, JP;

Kazuhiro Abe, Saitama, JP;

Tetsuya Yonemoto, Saitama, JP;

Kenji Ishihara, Saitama, JP;

Syunji Aoki, Saitama, JP;

Fumio Matsumoto, Saitama, JP;

Takanori Arai, Saitama, JP;

Hisashi Naoshima, Saitama, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K003/34 ; B23K031/02 ;
U.S. Cl.
CPC ...
Abstract

An electronics packaging system () including a printer (), a placing unit () and a reflow unit (), wherein a printed wiring board () is carried while being kept in an upright position. The printed wiring board () has solder printed on all the lands thereof at the same time, the electronic parts () are all placed on the lands at the same time, and the electronic parts () are all soldered to the lands at the same time. Thus, the system () can be designed more compact, and the electronic parts packaged in a shorter time.


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