Saitama, Japan

Katsumi Togasaki

This inventor holds 1 USPTO granted patent. Top assignee: Sony Corporation. Active years: 2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Katsumi Togasaki. Retrieved from https://idiyas.com/inventor/katsumi-togasaki

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 17.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2005

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1 patent (USPTO):Explore Patents

Title: Innovations by Katsumi Togasaki

Introduction

Katsumi Togasaki is a notable inventor based in Saitama, Japan. He has made significant contributions to the field of electronics packaging. His innovative approach has led to the development of a unique system that enhances the efficiency of electronic device mounting.

Latest Patents

Katsumi Togasaki holds a patent for a "System for mounting electronic device." This electronics packaging system includes a printer, a placing unit, and a reflow unit. The system allows a printed wiring board to be carried while being kept in an upright position. Solder is printed on all the lands of the board simultaneously, and electronic parts are placed and soldered to the lands at the same time. This design results in a more compact system and reduces the time required for packaging electronic parts.

Career Highlights

Katsumi Togasaki is currently employed at Sony Corporation, where he continues to innovate in the electronics sector. His work has been instrumental in advancing the technology used in electronic device manufacturing.

Collaborations

Some of his coworkers include Katsumi Morita and Mitsuo Inoue, who contribute to the collaborative environment at Sony Corporation.

Conclusion

Katsumi Togasaki's contributions to electronics packaging demonstrate his innovative spirit and commitment to improving manufacturing processes. His patent reflects a significant advancement in the efficiency of electronic device assembly.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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