The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2003
Filed:
Mar. 10, 2001
Arne W. Ballantine, Round Lake, NY (US);
Kevin K. Chan, Staten Island, NY (US);
Jeffrey D. Gilbert, Burlington, VT (US);
Kevin M. Houlihan, Boston, MA (US);
Glen L. Miles, Essex Junction, VT (US);
James J. Quinlivan, Essex Junction, VT (US);
Samuel C. Ramac, Poughkeepsie, NY (US);
Michael B. Rice, Colchester, VT (US);
Beth A. Ward, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.