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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6632278 B1

PDFFull Text
Date of Patent:
Oct. 14, 2003

Filed:

Apr. 30, 2002

Low defect density epitaxial wafer and a process for the preparation thereof

Applicant:
Inventors:

Robert A. Falster, London, GB;

Joseph C. Holzer, St. Charles, MO (US);

Steve A. Markgraf, Chandler, AZ (US);

Paolo Mutti, Milan, IT;

Seamus A. McQuaid, Victoria, ES;

Bayard K. Johnson, Jefferson Hills, PA (US);

Assignee:

MEMC Electronic Materials, Inc., St. Peters, MO (US);

Attorney:

Senniger, Powers, Leavitt & Roedel

Primary Examiner:

Robert Kunemund

Int. Cl.
CPC ...
C30B 2/906 ; C30B 2/500 ;
U.S. Cl.
CPC ...
C30B 2/906 ; C30B 2/500 ;
Abstract

The present invention relates to an epitaxial wafer comprising single crystal silicon substrate and an epitaxial layer deposited thereon. The substrate comprises an axially symmetric region which is free of agglomerated intrinsic point defects and wherein silicon self-interstitials are the predominant intrinsic point defect in the axially symmetric region. The present invention further relates to a process for producing such an epitaxial wafer.

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Falster, Robert. (2003). Low defect density epitaxial wafer and a process for the preparation thereof (U.S. Patent No. 6632278). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6632278

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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