The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2002

Filed:

Jan. 28, 2002
Applicant:
Inventors:

Hyeong-Seob Kim, Chungcheongnam-do, KR;

Sa-Yoon Kang, Seoul, KR;

Myung-Kee Chung, Chungcheongnam-do, KR;

In-Ku Kang, Chungcheongnam-do, KR;

Kwan-Jai Lee, Chungcheongnam-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/348 ; H01L 2/352 ; H01L 2/940 ;
U.S. Cl.
CPC ...
H01L 2/348 ; H01L 2/352 ; H01L 2/940 ;
Abstract

A three-dimensional, multi-chip package with chip selection pads formed at the chip-level and a manufacturing method thereof are provided. The three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, (N−1) chip selection pads, an insulation layer, (N−1) metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

Published as:
KR20020066095A; US2002109236A1; US6448661B1; JP2002305283A; KR100364635B1; JP4519392B2;

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