The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2001
Filed:
Dec. 03, 1998
Chandrika Prasad, Wappingers Falls, NY (US);
Roy Yu, Poughkeepsie, NY (US);
Richard L. Canull, Pleasant Valley, NY (US);
Giulio DiGiacomo, Hopewell Junction, NY (US);
Ajay P. Giri, Poughkeepsie, NY (US);
Lewis S. Goldmann, Bedford, NY (US);
Kimberley A. Kelly, Poughkeepsie, NY (US);
Bouwe W. Leenstra, Walden, NY (US);
Voya R. Markovich, Broome, NY (US);
Eric D. Perfecto, Poughkeepsie, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Joseph M. Sullivan, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure for mounting electronic devices which uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.