The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 1989
Filed:
Mar. 17, 1987
Yoshimi Shioya, Kuwana, JP;
Yasushi Oyama, Kodaira, JP;
Norihisa Tsuzuki, Higashimurayama, JP;
Mamoru Maeda, Tama, JP;
Masaaki Ichikawa, Hiratsuka, JP;
Fumitake Mieno, Kawasaki, JP;
Shin-ichi Inoue, Kawasaki, JP;
Yasuo Uo-ochi, Tokyo, JP;
Akira Tabuchi, Kawasaki, JP;
Atsuhiro Tsukune, Kawasaki, JP;
Takuya Watanabe, Sagamihara, JP;
Takayuki Ohba, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A method of selectively depositing tungsten upon a silicon semiconductor substrate. A silicon substrate is coated with a masking film of PSG or SiO.sub.2 that is patterned to provide an opening for forming an electrode or wiring. On a portion of the substrate in the opening, a layer of tungsten having a thickness of approximately 2000 .ANG. is deposited by a CVD method from an atomosphere containing a gaseous mixture of WF.sub.6 and H.sub.2 . During this processing, tungsten nucleuses deposit on the surface of the masking film as well. Before such nucleuses form a film, the deposition processing is discontinued and H.sub.2 gas is fed into the CVD apparatus to produce HF, which etches the surface of the masking film, and thus tungsten nucleuses are removed. The deposition and removal steps are repeated several times until the height of the deposited tungsten and the thickness of the masking film are essentially equal to present a flat surface. Aluminum film is deposited on the flat surface and patterned by lithography. The flat aluminum deposition allows fabrication of accurate and reliable wirings and facilitates production of VLSI of sub-micron order.