The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2026
Filed:
Mar. 22, 2023
Intel Corporation, Santa Clara, CA (US);
Tao Chu, Portland, OR (US);
Yanbin Luo, Portland, OR (US);
Yusung Kim, Portland, OR (US);
Minwoo Jang, Portland, OR (US);
Paul Packan, Hillsboro, OR (US);
Guowei Xu, Portland, OR (US);
Chiao-Ti Huang, Portland, OR (US);
Robin Chao, Portland, OR (US);
Feng Zhang, Hillsboro, OR (US);
Yang Zhang, Rio Rancho, NM (US);
Zheng Guo, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An IC device may have layout with reduced N-P boundary effect. The IC device may include two rows of transistors. The first row may include one or more P-type transistors. The second row may include N-type transistors. The gate electrode of a P-type transistor may include different conductive materials from the gate electrode of a N-type transistor. Each P-type transistor in the first row may be over a N-type transistor in the second row and contact the N-type transistor in the second row. For instance, the gate of the P-type transistor may contact the gate of the N-type transistor. Vacancy diffusion may occur at the boundary of the P-type transistor and the N-type transistor, causing N-P boundary effect. At least one or more other N-type transistors in the second row do not contact any P-type transistor, which can mitigate the N-P boundary effect in the IC device.