Portland, OR, United States of America

Yanbin Luo

This inventor holds 2 USPTO granted patents and 46 published patent applications. Top assignee: Intel Corporation. Active years: 2026.

USPTO Granted Patents = 2 

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Yanbin Luo - Innovator in Integrated Circuit Technologies

Introduction

Yanbin Luo is an inventor based in Portland, OR (US), known for his contributions to the field of integrated circuit (IC) devices. His work focuses on optimizing transistor performance and enhancing the uniformity of front-end structures in IC technology. Although he currently holds no granted patents, his innovative ideas are reflected in his latest patent applications.

Latest Patent Applications

1. **TRANSISTOR METALLIZATION ENDCAP SCALING FOR PERFORMANCE OPTIMIZATION**

This application describes integrated circuit (IC) devices featuring transistors with electrodes and/or contacts positioned in close proximity. The design includes a transistor structure with a channel between a source and a drain, a gate electrode over the channel region, and contacts on the source and drain. Notably, the electrode and contacts extend past the edge or sidewall of the channel at different distances, resulting in unaligned ends. The application also discusses how one or both of the source and drain contacts may extend past the gate electrode, and how the gate electrode may extend past one or both of the source and drain contacts. The dimensions of these components can be formed to unaligned specifications or adjusted through trimming.

2. **BACKSIDE ETCH PROCESSES FOR ULTRA UNIFORMITY OF FRONT-END STRUCTURES**

This application focuses on isolation structures between transistors in integrated circuit (IC) devices. It describes an IC device that includes transistors connected to an interconnect network, with a dielectric structure positioned between the transistors. This structure features a wider width away from the interconnect network and a narrower width closer to it. The application highlights how dielectric structures with wider back-side widths can effectively separate gate electrodes and/or source and drain contacts of the transistors. The formation of these dielectric structures involves etching an opening between metallization structures of the transistors from the back side of the device substrate, followed by the deposition of liner and fill dielectrics over the back-side opening.

Conclusion

Yanbin Luo is an innovative inventor whose latest patent applications demonstrate his commitment to advancing integrated circuit technologies. His work in optimizing transistor performance and enhancing uniformity in IC devices showcases his potential impact on the field.

Profile summary based on public USPTO records.
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