The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2026
Filed:
Aug. 19, 2022
Intel Corporation, Santa Clara, CA (US);
Adel Elsherbini, Chandler, AZ (US);
Lance C. Hibbeler, Tillamook, OR (US);
Omkar Karhade, Chandler, AZ (US);
Chytra Pawashe, Portland, OR (US);
Kimin Jun, Portland, OR (US);
Feras Eid, Chandler, AZ (US);
Shawna Liff, Scottsdale, AZ (US);
Mohammad Enamul Kabir, Portland, OR (US);
Bhaskar Jyoti Krishnatreya, Hillsboro, OR (US);
Tushar Talukdar, Wilsonville, OR (US);
Wenhao Li, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.