The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
Jun. 30, 2022
Intel Corporation, Santa Clara, CA (US);
Suddhasattwa Nad, Chandler, AZ (US);
Steve Cho, Chandler, AZ (US);
Marcel Arlan Wall, Phoenix, AZ (US);
Onur Ozkan, Scottsdale, AZ (US);
Ali Lehaf, Chandler, AZ (US);
Yi Yang, Gilbert, AZ (US);
Jason Scott Steill, Phoenix, AZ (US);
Gang Duan, Chandler, AZ (US);
Brandon C. Marin, Gilbert, AZ (US);
Jeremy D Ecton, Gilbert, AZ (US);
Srinivas Venkata Ramanuja Pietambaram, Chandler, AZ (US);
Haifa Hariri, Phoenix, AZ (US);
Bai Nie, Chandler, AZ (US);
Hiroki Tanaka, Chandler, AZ (US);
Kyle Mcelhinny, Tempe, AZ (US);
Jason Gamba, Gilbert, AZ (US);
Venkata Rajesh Saranam, Phoenix, AZ (US);
Kristof Darmawikarta, Chandler, AZ (US);
Haobo Chen, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.