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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12717998 B1

PDFFull Text
Date of Patent:
Aug. 25, 2026

Filed:

Jun. 05, 2023

Power routing reduction in circuit design for electrostatic discharge checking

Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Nicholas Stewart Palmer, Beaverton, OR (US);

Chih Yi Huang, New Taipei City, TW;

De-Shiuan Chiou, Taipei City, TW;

Yu-Chen Lin, Taoyuan City, TW;

Jeffrey Ellis Byrd, Greensboro, NC (US);

Charles Samuel Mcfalls, Jr., Graham, NC (US);

Chi Lo, New Taipei City, TW;

Chi-Chun Chuang, Taipei City, TW;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:

Weaver Austin Villeneuve & Sampson LLP

Primary Examiner:

Brian Ngo

Int. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01);
Abstract

A method for performing a computation associated with a layout of a circuit design includes, in part: generating a graph having a multitude of nodes disposed across a multitude of layers associated with the layout, wherein each node corresponds to a polygon in the layout, wherein the multitude of nodes includes a source node and a sink node; traversing from the source node to the sink node via the nodes in accordance with a rule enabling traversal between one or more of (i) nodes disposed in the same layer, and (ii) from a first node disposed in one of the layers to a node disposed in another layer that is higher than the first layer; pruning nodes that are not visited during the traversal; and maintaining nodes that are not pruned for use in the computation.

Find Patent Forward Citations

Palmer, Nicholas. (2026). Power routing reduction in circuit design for electrostatic discharge checking (U.S. Patent No. 12717998). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12717998

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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