This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Yu-Chen Lin and Power Routing Reduction in Circuit Design
Introduction
Yu-Chen Lin is an inventor associated with Taoyuan City, Taiwan, and Synopsys, Inc. Her work includes a patent addressing power-routing reduction for electrostatic discharge checking in circuit design. Lin is credited with 1 patent.
Latest Patents
Lin’s patent, “Power Routing Reduction in Circuit Design for Electrostatic Discharge Checking,” describes a method for analyzing a circuit layout. The method generates a graph whose nodes represent layout polygons across multiple layers, then traverses the graph from a source node to a sink node according to rules for movement within and between layers. It prunes nodes not visited during traversal and retains the remaining nodes for use in the computation. This approach is directed at reducing the routing considered during electrostatic discharge checks.
Career Highlights
Lin’s listed patent reflects work on circuit-design analysis and electrostatic discharge checking. Her professional affiliation is Synopsys, Inc., a company associated with electronic design automation and semiconductor design tools.
Collaborations
Lin’s listed coworkers include Nicholas Stewart Palmer and Chih Yi Huang. The available information identifies them as coworkers but does not specify their roles in the patent.
Conclusion
Yu-Chen Lin’s patent describes a graph-based method for streamlining circuit-layout analysis during electrostatic discharge checking, highlighting her contribution to electronic design automation.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
