Beaverton, OR, United States of America

Nicholas Stewart Palmer

This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nicholas Stewart Palmer. Retrieved from https://idiyas.com/inventor/nicholas-stewart-palmer

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Nicholas Stewart Palmer: Patent Inventor in Circuit Design

Introduction

Nicholas Stewart Palmer is an inventor based in Beaverton, Oregon. His patent work addresses circuit-design methods for electrostatic discharge checking, an important part of evaluating integrated-circuit layouts.

Latest Patents

Palmer is associated with 1 patent, titled “Power Routing Reduction in Circuit Design for Electrostatic Discharge Checking.” The patent describes a method that represents a circuit layout as a graph, with nodes corresponding to polygons across multiple layers. The method traverses the graph from a source node to a sink node according to specified layer-traversal rules, prunes nodes not visited, and retains the remaining nodes for use in a computation. This approach can reduce the power-routing data considered during electrostatic discharge checking.

Career Highlights

Palmer is associated with Synopsys, Inc., a company that develops software and services for semiconductor design and verification. His patent reflects work on improving circuit-layout analysis through graph traversal and selective pruning.

Collaborations

Palmer’s listed coworker is Chih Yi Huang. Their association provides context for the professional environment connected with the patent, though the supplied information does not specify their individual contributions or the nature of their collaboration.

Conclusion

Nicholas Stewart Palmer’s patent focuses on reducing the nodes considered in circuit-layout computations for electrostatic discharge checking, highlighting a practical approach to semiconductor design analysis.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…