De-Shiuan Chiou

Title: De-Shiuan Chiou: Innovator in Circuit Design Verification

Introduction

De-Shiuan Chiou is an inventor based in Taipei, Taiwan, whose work focuses on electronic design automation and circuit-layout verification. He is associated with Synopsys, Inc. His patent portfolio includes 2 patents addressing electrostatic discharge (ESD) protection and circuit-design analysis.

Latest Patents

Chiou’s listed patents describe methods and tools for improving ESD-related circuit verification.

“Power Routing Reduction in Circuit Design for Electrostatic Discharge Checking” presents a method for analyzing a circuit layout through a graph of nodes representing polygons across design layers. The method traverses the graph from a source node to a sink node according to specified layer and connectivity rules, prunes nodes that are not visited, and retains the remaining nodes for computation.

“Fixing ESD Path Resistance Errors in Circuit Design Layout” describes a physical-verification tool for diagnosing resistance violations in ESD ground paths. It models the path as component structures distributed across design layers, calculates total resistance, and compares the result with a limit set by an ESD protection rule. When the path fails the check, the tool identifies polygons or layers with high resistance contributions and produces a report that highlights the most problematic areas.

Career Highlights

Chiou’s patent work addresses practical challenges in verifying circuit layouts, including reducing unnecessary routing analysis and helping engineers locate sources of excessive ESD path resistance. These approaches support more focused debugging within electronic design workflows.

Collaborations

The supplied information identifies Yu-Chen Lin and Charles Samuel McFalls, Jr. as Chiou’s coworkers. It does not specify whether they collaborated with him on the listed patents.

Conclusion

De-Shiuan Chiou’s inventions focus on making ESD circuit verification more efficient and actionable through graph-based analysis and resistance diagnostics.