This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Chi Lo and His Patent in Circuit Design
Introduction
Chi Lo is an inventor associated with New Taipei City, Taiwan, and Synopsys, Inc. His patent work addresses circuit-design methods for electrostatic discharge checking.
Latest Patents
The available information lists one patent for Chi Lo: “Power Routing Reduction in Circuit Design for Electrostatic Discharge Checking.” The invention describes a method that generates a graph representing polygons across the layers of a circuit layout, then traverses the graph from a source node to a sink node according to specified layer and connectivity rules. It prunes nodes not visited during traversal and retains the remaining nodes for use in the computation. This approach is intended to reduce the power-routing information considered during electrostatic discharge checking. Chi Lo is credited with 1 patent.
Career Highlights
Chi Lo’s listed patent connects his work with electronic design automation and circuit-layout analysis at Synopsys, Inc. The method focuses on organizing and reducing graph data used in a design-checking computation.
Collaborations
The provided information names Nicholas Stewart Palmer and Chih Yi Huang as Chi Lo’s coworkers. Their inclusion indicates professional connections, but the available details do not specify their roles in the patent.
Conclusion
Chi Lo’s listed invention applies graph traversal and pruning to circuit-layout analysis, offering a focused method for supporting electrostatic discharge checking.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile